Difference between revisions of "Minimig Board v1.0 signaling"

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(Signaling scheme)
 
 
(3 intermediate revisions by the same user not shown)
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minimig1_firmware_15_07_2007/hardware.h<br>
 
minimig1_firmware_15_07_2007/hardware.h<br>
 +
:MCU: _F_CSx = FPGA spix select
  
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{| class="wikitable"
+
:{| class="wikitable"
 
|-  
 
|-  
−
! MCU Pin !! MCU Name !! MCU definition  !! MCU Comment      !! Comment
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! Signal !! MCU Pin !! MCU Name !! FPGA pin !! FPGA name !! Description
 
|-
 
|-
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|  3 || RA1 || _F_CS0 || FGPA spi0 select || EnableFpga() _F_CS0=0
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| /FPGA_SEL0 ||  3 || RA1 || 93 || IO          || EnableFpga() _F_CS0=0
 
|-
 
|-
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| 26 || RB5 || _F_CS1 || FGPA spi1 select || EnableOsd()  _F_CS1=0
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| /FPGA_SEL1 || 26 || RB5 || 86 || IO_L30P_4/D3 || EnableOsd()  _F_CS1=0
 
|-
 
|-
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| 27 || RB6 || _F_CS2 || FGPA spi2 select ||
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| /FPGA_SEL2 || 27 || RB6 || 87 || IO_L30N_4/D2 || 
 +
|}
 +
 
 +
FPGA <-> MCU interface consist of:
 +
:{| class="wikitable"
 +
|-
 +
! Signal !! MCU dir !! SD/MMC dir !! FPGA dir !! Description
 +
|-
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| SPI_CLK  || Out || In  || In || Clock
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|-
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| SPI_DIN  || Out || In  || In || Data
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|-
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| SPI_DOUT || In  || Out || Out || Data 
 
|}
 
|}

Latest revision as of 16:29, 26 August 2007

minimig1_firmware_15_07_2007/hardware.h

MCU: _F_CSx = FPGA spix select
Signal MCU Pin MCU Name FPGA pin FPGA name Description
/FPGA_SEL0 3 RA1 93 IO EnableFpga() _F_CS0=0
/FPGA_SEL1 26 RB5 86 IO_L30P_4/D3 EnableOsd() _F_CS1=0
/FPGA_SEL2 27 RB6 87 IO_L30N_4/D2

FPGA <-> MCU interface consist of:

Signal MCU dir SD/MMC dir FPGA dir Description
SPI_CLK Out In In Clock
SPI_DIN Out In In Data
SPI_DOUT In Out Out Data
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