Difference between revisions of "Minimig Board v1.0 signaling"

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(fpga def)
Line 1: Line 1:
 
minimig1_firmware_15_07_2007/hardware.h<br>
 
minimig1_firmware_15_07_2007/hardware.h<br>
 +
MCU: _F_CSx = FPGA spix select
  
 
{| class="wikitable"
 
{| class="wikitable"
 
|-  
 
|-  
! MCU Pin !! MCU Name !! MCU definition  !! MCU Comment      !! Comment
+
! Signal !! MCU Pin !! MCU Name !! FPGA pin !! FPGA name !! Description
 
|-
 
|-
|  3 || RA1 || _F_CS0 || FGPA spi0 select || EnableFpga() _F_CS0=0
+
| /FPGA_SEL0 ||  3 || RA1 || 93 || IO          || EnableFpga() _F_CS0=0
 
|-
 
|-
| 26 || RB5 || _F_CS1 || FGPA spi1 select || EnableOsd()  _F_CS1=0
+
| /FPGA_SEL1 || 26 || RB5 || 86 || IO_L30P_4/D3 || EnableOsd()  _F_CS1=0
 
|-
 
|-
| 27 || RB6 || _F_CS2 || FGPA spi2 select ||
+
| /FPGA_SEL2 || 27 || RB6 || 87 || IO_L30N_4/D2 ||
 
|}
 
|}

Revision as of 21:37, 24 August 2007

minimig1_firmware_15_07_2007/hardware.h
MCU: _F_CSx = FPGA spix select

Signal MCU Pin MCU Name FPGA pin FPGA name Description
/FPGA_SEL0 3 RA1 93 IO EnableFpga() _F_CS0=0
/FPGA_SEL1 26 RB5 86 IO_L30P_4/D3 EnableOsd() _F_CS1=0
/FPGA_SEL2 27 RB6 87 IO_L30N_4/D2