Editing Minimig Board v1.0 schematic
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| − | Board schematic for Minimig board v1.0 | + | Board schematic for Minimig board v1.0 |
[[Image:Minimig_v10_board_audio.png|thumb|right|250px|J1 - Audio output via 3,5mm jack]] | [[Image:Minimig_v10_board_audio.png|thumb|right|250px|J1 - Audio output via 3,5mm jack]] | ||
| + | Voltage level: (3.3V/(560ohm + 560ohm + 32ohm))*32 ohm*1000 = 91,7mV<br> | ||
| + | [[Back EMF]] issues?<br> | ||
| + | [http://en.wikipedia.org/wiki/Headphone Head phones]<br> | ||
| + | |||
[[Image:Minimig_v10_board_dac.png|thumb|right|250px|J4 - 4 bit resistor ladder D/A]] | [[Image:Minimig_v10_board_dac.png|thumb|right|250px|J4 - 4 bit resistor ladder D/A]] | ||
| − | + | Notice the resistor of 560 ohm. May cause inlinear output.<br> | |
| + | :in 15kHz mode: | ||
:/VSYNC = high (scart RGB enable) | :/VSYNC = high (scart RGB enable) | ||
:/HSYNC = composite sync | :/HSYNC = composite sync | ||
[[Image:Minimig_v10_board_fpga.png|thumb|right|250px|IC5 - [[FPGA]] Xilinx XC3S400-4PQ208C]] | [[Image:Minimig_v10_board_fpga.png|thumb|right|250px|IC5 - [[FPGA]] Xilinx XC3S400-4PQ208C]] | ||
| + | |||
[[Image:Minimig_v10_board_fpga_core_pwr.png|thumb|right|250px|IC3/IC4 - FPGA core power +1,25V +2,5V using [http://www.national.com/pf/LM/LM1117.html LM1117MP-ADJ] ]] | [[Image:Minimig_v10_board_fpga_core_pwr.png|thumb|right|250px|IC3/IC4 - FPGA core power +1,25V +2,5V using [http://www.national.com/pf/LM/LM1117.html LM1117MP-ADJ] ]] | ||
| + | |||
[[Image:Minimig_v10_board_fpga_decoupling.png|thumb|right|250px|FPGA [[decoupling]]]] | [[Image:Minimig_v10_board_fpga_decoupling.png|thumb|right|250px|FPGA [[decoupling]]]] | ||
[[Image:Minimig_v10_board_joy0.png|thumb|right|250px|J10 - Joystick 0]] | [[Image:Minimig_v10_board_joy0.png|thumb|right|250px|J10 - Joystick 0]] | ||
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:Disconnect net SPI_DOUT from pin 81 of FPGA. | :Disconnect net SPI_DOUT from pin 81 of FPGA. | ||
:Connect net SPI_DOUT to pin 19 of FPGA (net USER3). | :Connect net SPI_DOUT to pin 19 of FPGA (net USER3). | ||
| − | :REASON: Pin 81 is an output during FPGA config that blocks SPI to MMC during startup. | + | : |
| + | :REASON: | ||
| + | :Pin 81 is an output during FPGA config that blocks SPI to MMC during startup. | ||
[[Image:Minimig_v10_board_pic18.png|thumb|right|250px|IC10 - [[MCU]] [http://ww1.microchip.com/downloads/en/devicedoc/39564b.pdf PIC18LF252I/SP] (DIP28)]] | [[Image:Minimig_v10_board_pic18.png|thumb|right|250px|IC10 - [[MCU]] [http://ww1.microchip.com/downloads/en/devicedoc/39564b.pdf PIC18LF252I/SP] (DIP28)]] | ||
| + | |||
[[Image:Minimig_v10_board_ram512x16.png|thumb|right|250px|IC6/IC7 - [[Asynchronous static ram]] 512 x 16 bit (2 chips)]] | [[Image:Minimig_v10_board_ram512x16.png|thumb|right|250px|IC6/IC7 - [[Asynchronous static ram]] 512 x 16 bit (2 chips)]] | ||
| + | |||
[[Image:Minimig_v10_board_rs232.png|thumb|right|250px|IC2 - Serial [[RS232]] using [http://datasheets.maxim-ic.com/en/ds/MAX220-MAX249.pdf MAX232A] (SO16), output J3]] | [[Image:Minimig_v10_board_rs232.png|thumb|right|250px|IC2 - Serial [[RS232]] using [http://datasheets.maxim-ic.com/en/ds/MAX220-MAX249.pdf MAX232A] (SO16), output J3]] | ||
[[Image:Minimig_v10_board_main_pwr.png|thumb|right|250px|IC1 - Main power supply]] | [[Image:Minimig_v10_board_main_pwr.png|thumb|right|250px|IC1 - Main power supply]] | ||
| + | |||
[[Image:Minimig_v10_board_sd_card.png|thumb|right|250px|J11 - [[SD Card]] slot]] | [[Image:Minimig_v10_board_sd_card.png|thumb|right|250px|J11 - [[SD Card]] slot]] | ||
[[Image:Minimig_v10_board_spare_io.png|thumb|right||J9 - Spare I/O directly connected to FPGA]]<br> | [[Image:Minimig_v10_board_spare_io.png|thumb|right||J9 - Spare I/O directly connected to FPGA]]<br> | ||
| + | <br> | ||
| + | [http://www.xilinx.com/ise/products/webpack_config.htm Xilinx ISE Webpack device support]<br> | ||
