Difference between revisions of "Ethernet PHY STE100P"

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(comments)
(comments + required col)
 
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{| class="wikitable"
 
{| class="wikitable"
 
|-  
 
|-  
−
! Pin !! Name !! Direction !! Comment
+
! Pin !! Name !! Direction !! Required !! Comment
 
|-
 
|-
−
| 52 || TXD4 || I || Data
+
| 52 || TXD4 || I ||  
 
|-
 
|-
−
| 58 || TXD3 || I
+
| 58 || TXD3 || I || X || Data
 
|-
 
|-
−
| 57 || TXD2 || I
+
| 57 || TXD2 || I || X
 
|-
 
|-
−
| 56 || TXD1 || I
+
| 56 || TXD1 || I || X
 
|-
 
|-
−
| 55 || TXD0 || I
+
| 55 || TXD0 || I || X
 
|-
 
|-
−
| 54 || TX_EN || I || Valid
+
| 54 || TX_EN || I || X || Valid
 
|-
 
|-
−
| 53 || TX_CLK || I/O || Clock
+
| 53 || TX_CLK || I/O || || Clock
 
|-
 
|-
−
| 52 || TX_ER || I || Error
+
| 52 || TX_ER || I || || Error
 
|-
 
|-
 
|   || ||
 
|   || ||
 
|-
 
|-
−
| 51 || RXD4 || O
+
| 51 || RXD4   || O
 
|-
 
|-
−
| 43 || RXD3 || O
+
| 43 || RXD3   || O || X
 
|-
 
|-
−
| 44 || RXD2 || O
+
| 44 || RXD2   || O || X
 
|-
 
|-
−
| 46 || RXD1 || O
+
| 46 || RXD1   || O || X
 
|-
 
|-
−
| 47 || RXD0 || O
+
| 47 || RXD0   || O || X
 
|-
 
|-
−
| 48 || RX_DV || O
+
| 48 || RX_DV || O || X
 
|-
 
|-
−
| 51 || RX_ER || O
+
| 51 || RX_ER || O ||
 
|-
 
|-
−
| 49 || RX_CLK || O
+
| 49 || RX_CLK || O ||
 
|-
 
|-
 
|   || ||
 
|   || ||
 
|-
 
|-
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| 59 || COL || O || Collision Detected.
+
| 59 || COL || O || || Collision Detected.
 
|-
 
|-
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| 60 || CRS || O || Carrier Sense.
+
| 60 || CRS || O || || Carrier Sense.
 
|-
 
|-
 
|   || ||
 
|   || ||
 
|-
 
|-
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| 42 || MDC || I    || Clock
+
| 42 || MDC || I    || || Clock
 
|-
 
|-
−
| 41 || MDIO || I/O  || Data I/O
+
| 41 || MDIO || I/O  || || Data I/O
 
|-
 
|-
−
| 61 || MDINT || OD  || Interrupt
+
| 61 || MDINT || OD  || || Interrupt
 
|-
 
|-
 
|   || ||
 
|   || ||
 
|-
 
|-
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| 12 || X1 || I || 25 MHz reference clock input.
+
| 12 || X1 || I || || 25 MHz reference clock input.
 
|-
 
|-
−
| 11 || X2 || O ||
+
| 11 || X2 || O || ||
 
|-
 
|-
 
| 21 || TXP || O
 
| 21 || TXP || O
Line 65: Line 65:
 
| 18 || RXN || I
 
| 18 || RXN || I
 
|-
 
|-
−
| 15 || IREF || O || 5k 1% resistor to Vss.
+
| 15 || IREF || O || || 5k 1% resistor to Vss.
 
|-
 
|-
−
| 38 || LEDR10 || I/O || 10Base-T used.
+
| 38 || LEDR10 || I/O || || 10Base-T used.
 
|-
 
|-
−
| 37 || LEDTR || || 10 Hz Activity status.
+
| 37 || LEDTR || || || 10 Hz Activity status.
 
|-
 
|-
−
| 36 || LEDL || I/O || Link Status.
+
| 36 || LEDL || I/O || || Link Status.
 
|-
 
|-
−
| 35 || LEDC || I/O || Full Duplex or Collision status.
+
| 35 || LEDC || I/O || || Full Duplex or Collision status.
 
|-
 
|-
−
| 34 || LEDS || I/O || 100Base-T used.
+
| 34 || LEDS || I/O || || 100Base-T used.
 
|-
 
|-
 
| 64 || CFG0 || I
 
| 64 || CFG0 || I
Line 83: Line 83:
 
| 28 || RESET || I
 
| 28 || RESET || I
 
|-
 
|-
−
| 29 || RIP || O || Reset In Progress.
+
| 29 || RIP || O || || Reset In Progress.
 
|-
 
|-
−
| 8,30,31,32 || NC ||  
+
| 8,30,31,32 || NC || ||
 
|-
 
|-
 
| 26 || TEST ||  
 
| 26 || TEST ||  
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| 33 || TEST_SE ||  
 
| 33 || TEST_SE ||  
 
|-
 
|-
−
| 27 || PWRDWN || I
+
| 27 || PWRDWN || I ||
 
|-
 
|-
−
| 05 || MF0 || I || Auto-Negotiation
+
| 05 || MF0 || I || || Auto-Negotiation
 
|-
 
|-
−
| 04 || MF1 || I || Enable NRZ-NRZI conversion
+
| 04 || MF1 || I || || Enable NRZ-NRZI conversion
 
|-
 
|-
−
| 03 || MF2 || I || 4B/5B Coding enable
+
| 03 || MF2 || I || || 4B/5B Coding enable
 
|-
 
|-
−
| 02 || MF3 || I || Scrambler Operation Disable
+
| 02 || MF3 || I || || Scrambler Operation Disable
 
|-
 
|-
−
| 01 || MF4 || I || MF4 10/100 Mbps Speed select
+
| 01 || MF4 || I || || MF4 10/100 Mbps Speed select
 
|-
 
|-
−
| 06 || FDE || I || Full-Duplex Enable.
+
| 06 || FDE || I || || Full-Duplex Enable.
 
|-
 
|-
 
| 39,45,62      || VCCE/I ||  
 
| 39,45,62      || VCCE/I ||  

Latest revision as of 19:32, 24 August 2007

Pin Name Direction Required Comment
52 TXD4 I
58 TXD3 I X Data
57 TXD2 I X
56 TXD1 I X
55 TXD0 I X
54 TX_EN I X Valid
53 TX_CLK I/O Clock
52 TX_ER I Error
 
51 RXD4 O
43 RXD3 O X
44 RXD2 O X
46 RXD1 O X
47 RXD0 O X
48 RX_DV O X
51 RX_ER O
49 RX_CLK O
 
59 COL O Collision Detected.
60 CRS O Carrier Sense.
 
42 MDC I Clock
41 MDIO I/O Data I/O
61 MDINT OD Interrupt
 
12 X1 I 25 MHz reference clock input.
11 X2 O
21 TXP O
23 TXN O
19 RXP I
18 RXN I
15 IREF O 5k 1% resistor to Vss.
38 LEDR10 I/O 10Base-T used.
37 LEDTR 10 Hz Activity status.
36 LEDL I/O Link Status.
35 LEDC I/O Full Duplex or Collision status.
34 LEDS I/O 100Base-T used.
64 CFG0 I
63 CFG1 I
28 RESET I
29 RIP O Reset In Progress.
8,30,31,32 NC
26 TEST
33 TEST_SE
27 PWRDWN I
05 MF0 I Auto-Negotiation
04 MF1 I Enable NRZ-NRZI conversion
03 MF2 I 4B/5B Coding enable
02 MF3 I Scrambler Operation Disable
01 MF4 I MF4 10/100 Mbps Speed select
06 FDE I Full-Duplex Enable.
39,45,62 VCCE/I
25 GNDE
40,50 GNDE/I
9,13,16,17,22 VCCA
7,10,14,20,24 GNDA
Direction Description
I External -> PHY
O PHY -> External
I/O Bidirectional
OD PHY -> External

STE100P - Single port fast ethernet phy / transceiver datasheet 070825 st.com

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