Editing Ethernet PHY STE100P
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{| class="wikitable" | {| class="wikitable" | ||
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− | ! Pin !! Name !! Direction | + | ! Pin !! Name !! Direction !! Comment |
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− | | 52 || TXD4 || I | + | | 52 || TXD4 || I || Data |
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− | | 58 || TXD3 || I | + | | 58 || TXD3 || I |
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− | | 57 || TXD2 || I | + | | 57 || TXD2 || I |
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− | | 56 || TXD1 || I | + | | 56 || TXD1 || I |
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− | | 55 || TXD0 || I | + | | 55 || TXD0 || I |
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− | | 54 || TX_EN || I | + | | 54 || TX_EN || I || Valid |
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− | | 53 || TX_CLK || I/O | + | | 53 || TX_CLK || I/O || Clock |
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− | | 52 || TX_ER || I | + | | 52 || TX_ER || I || Error |
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| || || | | || || | ||
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− | | 51 || RXD4 | + | | 51 || RXD4 || O |
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− | | 43 || RXD3 | + | | 43 || RXD3 || O |
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− | | 44 || RXD2 | + | | 44 || RXD2 || O |
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− | | 46 || RXD1 | + | | 46 || RXD1 || O |
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− | | 47 || RXD0 | + | | 47 || RXD0 || O |
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− | | 48 || RX_DV | + | | 48 || RX_DV || O |
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− | | 51 || RX_ER | + | | 51 || RX_ER || O |
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− | | 49 || RX_CLK || O | + | | 49 || RX_CLK || O |
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| || || | | || || | ||
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− | | 59 || COL || O | + | | 59 || COL || O || Collision Detected. |
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− | | 60 || CRS || O | + | | 60 || CRS || O || Carrier Sense. |
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| || || | | || || | ||
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− | | 42 || MDC || I | + | | 42 || MDC || I || Clock |
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− | | 41 || MDIO || I/O | + | | 41 || MDIO || I/O || Data I/O |
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− | | 61 || MDINT || OD | + | | 61 || MDINT || OD || Interrupt |
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| || || | | || || | ||
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− | | 12 || X1 || I | + | | 12 || X1 || I || 25 MHz reference clock input. |
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− | | 11 || X2 || O | + | | 11 || X2 || O || |
|- | |- | ||
| 21 || TXP || O | | 21 || TXP || O | ||
Line 65: | Line 65: | ||
| 18 || RXN || I | | 18 || RXN || I | ||
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− | | 15 || IREF || O | + | | 15 || IREF || O || 5k 1% resistor to Vss. |
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− | | 38 || LEDR10 || I/O | + | | 38 || LEDR10 || I/O || 10Base-T used. |
|- | |- | ||
− | | 37 || LEDTR | + | | 37 || LEDTR || || 10 Hz Activity status. |
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− | | 36 || LEDL || I/O | + | | 36 || LEDL || I/O || Link Status. |
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− | | 35 || LEDC || I/O | + | | 35 || LEDC || I/O || Full Duplex or Collision status. |
|- | |- | ||
− | | 34 || LEDS || I/O | + | | 34 || LEDS || I/O || 100Base-T used. |
|- | |- | ||
| 64 || CFG0 || I | | 64 || CFG0 || I | ||
Line 83: | Line 83: | ||
| 28 || RESET || I | | 28 || RESET || I | ||
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− | | 29 || RIP || O | + | | 29 || RIP || O || Reset In Progress. |
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− | | 8,30,31,32 || NC | + | | 8,30,31,32 || NC || |
|- | |- | ||
| 26 || TEST || | | 26 || TEST || | ||
Line 91: | Line 91: | ||
| 33 || TEST_SE || | | 33 || TEST_SE || | ||
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− | | 27 || PWRDWN || I | + | | 27 || PWRDWN || I |
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− | | 05 || MF0 || I | + | | 05 || MF0 || I || Auto-Negotiation |
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− | | 04 || MF1 || I | + | | 04 || MF1 || I || Enable NRZ-NRZI conversion |
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− | | 03 || MF2 || I | + | | 03 || MF2 || I || 4B/5B Coding enable |
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− | | 02 || MF3 || I | + | | 02 || MF3 || I || Scrambler Operation Disable |
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− | | 01 || MF4 || I | + | | 01 || MF4 || I || MF4 10/100 Mbps Speed select |
|- | |- | ||
− | | 06 || FDE || I | + | | 06 || FDE || I || Full-Duplex Enable. |
|- | |- | ||
| 39,45,62 || VCCE/I || | | 39,45,62 || VCCE/I || |