Difference between revisions of "Field-programmable gate array"
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| − | FPGA is a logic matrix configurable | + | A '''Field-Programmable Gate Array''' (FPGA) is a general purpose logic matrix configurable integrated circuit. It consists of a collection of logic gates that can be connected together in an almost unlimited number of combinations to produce custom operations that would normally only be possible with full-custom integrated circuits. Since FPGAs are produced in high volume, they can bring economies of scale to one-off and low volume projects. |
Several open hardware projects use FPGAs, such as | Several open hardware projects use FPGAs, such as | ||
* [[Minimig FPGA]] | * [[Minimig FPGA]] | ||
* ... | * ... | ||
| − | * [[ | + | * [[Motherboards that run Linux#Balloon_Xscale_ARM.2BFPGA_dev_board | Balloon Xscale + FPGA board]] |
| + | * [[RTL m68k]] | ||
* [[WikiNode | The Open Graphics Project]] (OGP) is developing graphics cards with fully published specs and open source drivers. Since the first version will be a FPGA, is also collecting information on FPGA programming and interfacing. | * [[WikiNode | The Open Graphics Project]] (OGP) is developing graphics cards with fully published specs and open source drivers. Since the first version will be a FPGA, is also collecting information on FPGA programming and interfacing. | ||
| + | * Icepi Zero by Chengyin Yao - An open-source portable FPGA development board in a Raspberry Pi Zero [[form factor]] (KiCAD): https://github.com/cheyao/icepi-zero ; https://hackaday.com/2025/05/29/icepi-zero-a-pi-zero-for-fpga/ | ||
| + | * 'Flea Ohm' FPGA Project by Valentin Angelovski - an FPGA backpack or hat for the Pi Zero (or can run standalone) in the Raspberry Pi Zero form factor: https://hackaday.io/project/13048-flea-ohm-fpga-project ; https://hackaday.com/2016/10/02/hackaday-prize-entry-fpgas-for-the-raspberry-pi-zero/ | ||
* ... | * ... | ||
* ... ''(Add other open hardware projects I'm forgetting to this list)'' | * ... ''(Add other open hardware projects I'm forgetting to this list)'' | ||
| Line 15: | Line 18: | ||
== Verilog == | == Verilog == | ||
| + | Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction. | ||
| + | |||
| + | == VHDL == | ||
| + | VHDL (VHSIC hardware description language) is commonly used as a design-entry language for designing digital circuits as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). | ||
| + | |||
| + | == History == | ||
| + | |||
| + | ... standard logic devices ... | ||
| + | |||
| + | The 1978 programmable array logic ([[PAL]]) was a revolutionary device. | ||
| + | Previous CPUs were built from a rack of PCBs full of of TTL ICs ([[standard logic CPU]]); | ||
| + | PALs allowed CPUs that were just as complex to be built from far fewer ICs on less than a dozen PCBs. | ||
| + | The book "Soul of a New Machine" described the development | ||
| + | of the "Eagle", one of the first CPUs to use PALs rather than fixed-function TTL ICs ([[TTL CPU]]).<ref> | ||
| + | [https://www.embeddedrelated.com/showthread/fpga-cpu/1193-1.php "PAL/GAL CPUs?"]. | ||
| + | </ref> | ||
| + | PAL chips were first introduced in 1978 by MMI (now part of Lattice Semiconductor) and soon second sourced by National Semiconductor, Texas Instruments and AMD. | ||
| − | + | GAL devices are direct replacements for most PAL, EPLD, and PEEL devices.<ref> | |
| + | Lattice Semiconductor. | ||
| + | [https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/CopyingPALEPLDandPEELPatternsintoGALDevices.ashx?la=en "Copying PAL, EPLD and PEEL Patterns into GAL Devices"]. | ||
| + | 2002. | ||
| + | </ref> | ||
| + | The advantage of GAL and PEEL is that they can be quickly erased and re-programmed, unlike PALs which have one-time-programmable fuses or EPLDs which can only slowly be erased with ultraviolet light through a glass window. | ||
| + | |||
| + | The ispGAL devices are a further improvement: they have JTAG port that supports in-system programmability (ISP), unlike earlier devices that need to be socketed to allow pulling them out of the system, then plugging in a freshly-programmed device. (That JTAG port also supports internal and board-level testing).<ref> | ||
| + | [https://www.latticesemi.com/support/answerdatabase/2/4/245 "What is the difference between an ispGAL and a GAL device?"] | ||
| + | </ref> | ||
| + | |||
| + | SPLDs ... | ||
| + | |||
| + | CPLDs ... further improve density ... | ||
| + | ... | ||
| + | FPGAs ... are even more dense -- entire CPUs can be implemented on a single FPGA IC. | ||
| + | Some FPGAs have enough capacity to implement multiple CPUs ... | ||
| + | but they have some drawbacks: | ||
| + | * most FPGAs reload their configuration on power-up, unlike CPLDs and SPLDs which are instant-on. | ||
| + | * CPLDs and SPLDs have more predictable timing delays | ||
| + | * SPLDs often have several second sources | ||
| + | * building something with some specific FPGA seems to force the designer to use one specific proprietary software tool on one of a narrow range of specific proprietary OSes.<ref> | ||
| + | Dieter Mueller 2004. | ||
| + | [http://www.6502.org/users/dieter/mt15/mt15.htm "MT15"]. | ||
| + | quote: "If there would be a standard with FPGAs/CPLDs | ||
| + | ... allowing me to select | ||
| + | between parts from different manufacturers with the | ||
| + | same Pin_out while still working with the same | ||
| + | (non_proprietary/open_source) software tools, | ||
| + | this project would not exist." | ||
| + | </ref> | ||
| + | * ... | ||
| − | + | GALs and CPLDs are still popular for retrocomputing projects | |
| + | * (a) handling address decoding and other glue logic for "classic" 8-bit processors such as the 6502 and Z80 | ||
| + | * (b) replacing the difficult-to-source 74181 and 74182 ALU chips used in many "discrete TTL CPUs", and perhaps further shrinking "discrete TTL CPUs" down to a few chips<ref> | ||
| + | [https://www.bigmessowires.com/cpu-in-a-cpld/ "Tiny CPU in a CPLD"]. | ||
| + | </ref><ref> | ||
| + | Jim Mussared. [https://github.com/jimmo/cpld-cpu "cpld-cpu: A simple CPU implemented by discrete CPLD components."]. | ||
| + | </ref><ref> | ||
| + | Jim Mussared. [https://blog.jimmo.id.au/2019/01/26/cpld-cpu-part-1.html "CPLD CPU: Part 1, Overview"]. | ||
| + | quote: "Unfortunately the ALU chips (74181 and 74182) proved hard to source". | ||
| + | quote: "However the idea is to make it possible to see what’s going on – every signal should have an LED on it." | ||
| + | </ref><ref> | ||
| + | Ed S. [https://hackaday.io/project/25357-opc-1-cpu-for-cpld "OPC-1 CPU for CPLD"]. | ||
| + | </ref><ref> | ||
| + | [https://github.com/cpldcpu/MCPU "MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD"]. | ||
| + | </ref> | ||
| − | + | Some open-source GAL programming tools (FIXME: very incomplete): | |
| + | Many people use a Jam STAPL player (running on a laptop or Raspberry Pi) to send the "hex file" over a JTAG port to program a ispGAL or a FPGAs: | ||
| + | * Marcel Groothuis : "Altera Jam STAPL Player with support for 64-bit Windows versions and Raspberry Pi" : https://github.com/margro/jam-stapl | ||
| + | * vladermolaev: "jam2ftdi: Customization of Altera Jam STAPL Byte-Code Player Version 2.5 to work over USB for devices built on FTDI chips." https://github.com/vladermolaev/jam2ftdi | ||
| + | * Muhammet Şükrü Demir: "jam_bc_player: Jam STAPL Byte-Code Player for in-app programming Altera devices in embedded systems... such as STM32 or similar MCUs" https://github.com/dsm/jam_bc_player | ||
| + | * steieio: "Altera JAM STAPL Player" : https://github.com/steieio/altera-jam-player | ||
| + | * "The Jam STAPL Byte-Code Player is coded in the C programming language for 16 bit and 32 bit processors. A specific subset of the player source code also supports some 8 bit processors." https://www.intel.com/content/www/us/en/docs/programmable/683089/current/the-jam-stapl-byte-code-player.html | ||
| + | * [https://web.archive.org/web/20020602040033/http://jamisp.com/ "the Jam STAPL Web Site"] (archived) | ||
| − | + | * [https://hackaday.com/2008/12/11/how-to-programmable-logic-devices-cpld/ "How-to: Programmable Logic Devices (CPLD)"]. | |
| + | * [https://www.bhabbott.net.nz/atfblast.html "Parallel Port ATF and GAL Programmer"]. | ||
| + | * Richard Steven Walz. [http://www.armory.com/~rstevew/Public/Pgmrs/GAL/algo.htm "GAL programming algorithms"]. | ||
| + | * [http://www.armory.com/%7Erstevew/Public/Pgmrs/GAL/_ClikMe1st.htm "Manfred Winterhoff's GALBlast"]. | ||
| + | * Rune Baeverrud and Woody Johnson. [http://www.pldworld.com/_altera/html/ref/freecore/nosupport/blaster.htm "Build your own ByteBlaster"]. | ||
| + | * http://www.pldworld.com/_altera/html/ref/freecore/nosupport/nosupport.html | ||
| + | * [https://elm-chan.org/works/pgal/report_e.html "Simple GAL Programmer"] 1999. Requires parallel port. Also programs PIC16F84. | ||
| + | == Further reading == | ||
* [http://en.wikipedia.org/wiki/Field-programmable_gate_array Wikipedia: field-programmable gate array] | * [http://en.wikipedia.org/wiki/Field-programmable_gate_array Wikipedia: field-programmable gate array] | ||
* [http://wiki.opengraphics.org/ The Open Graphics Project wiki]: The Open Graphics Project (OGP) is developing graphics cards with Free-licensed specifications and Free Software drivers. The FPGA development board OGD1, Revision B, uses a Xilinx® Spartan™-III XC3S4000 FPGA (primary FPGA) and a Lattice® LFXP10 non-volatile FPGA (PCI interface) | * [http://wiki.opengraphics.org/ The Open Graphics Project wiki]: The Open Graphics Project (OGP) is developing graphics cards with Free-licensed specifications and Free Software drivers. The FPGA development board OGD1, Revision B, uses a Xilinx® Spartan™-III XC3S4000 FPGA (primary FPGA) and a Lattice® LFXP10 non-volatile FPGA (PCI interface) | ||
* [http://wacco.mveas.com/ "Project VGA"]: Home of the Low Budget, Open Source, VGA Compatible video card. Uses Xilinx Spartan 3 s400 FPGA. | * [http://wacco.mveas.com/ "Project VGA"]: Home of the Low Budget, Open Source, VGA Compatible video card. Uses Xilinx Spartan 3 s400 FPGA. | ||
| − | |||
| − | |||
| − | |||
Latest revision as of 16:07, 18 June 2025
A Field-Programmable Gate Array (FPGA) is a general purpose logic matrix configurable integrated circuit. It consists of a collection of logic gates that can be connected together in an almost unlimited number of combinations to produce custom operations that would normally only be possible with full-custom integrated circuits. Since FPGAs are produced in high volume, they can bring economies of scale to one-off and low volume projects.
Several open hardware projects use FPGAs, such as
- Minimig FPGA
- ...
- Balloon Xscale + FPGA board
- RTL m68k
- The Open Graphics Project (OGP) is developing graphics cards with fully published specs and open source drivers. Since the first version will be a FPGA, is also collecting information on FPGA programming and interfacing.
- Icepi Zero by Chengyin Yao - An open-source portable FPGA development board in a Raspberry Pi Zero form factor (KiCAD): https://github.com/cheyao/icepi-zero ; https://hackaday.com/2025/05/29/icepi-zero-a-pi-zero-for-fpga/
- 'Flea Ohm' FPGA Project by Valentin Angelovski - an FPGA backpack or hat for the Pi Zero (or can run standalone) in the Raspberry Pi Zero form factor: https://hackaday.io/project/13048-flea-ohm-fpga-project ; https://hackaday.com/2016/10/02/hackaday-prize-entry-fpgas-for-the-raspberry-pi-zero/
- ...
- ... (Add other open hardware projects I'm forgetting to this list)
Verilog ... Xilinx ... Altera ... Lattice ...
Contents
Verilog
Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction.
VHDL
VHDL (VHSIC hardware description language) is commonly used as a design-entry language for designing digital circuits as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).
History
... standard logic devices ...
The 1978 programmable array logic (PAL) was a revolutionary device. Previous CPUs were built from a rack of PCBs full of of TTL ICs (standard logic CPU); PALs allowed CPUs that were just as complex to be built from far fewer ICs on less than a dozen PCBs. The book "Soul of a New Machine" described the development of the "Eagle", one of the first CPUs to use PALs rather than fixed-function TTL ICs (TTL CPU).<ref> "PAL/GAL CPUs?". </ref> PAL chips were first introduced in 1978 by MMI (now part of Lattice Semiconductor) and soon second sourced by National Semiconductor, Texas Instruments and AMD.
GAL devices are direct replacements for most PAL, EPLD, and PEEL devices.<ref> Lattice Semiconductor. "Copying PAL, EPLD and PEEL Patterns into GAL Devices". 2002. </ref> The advantage of GAL and PEEL is that they can be quickly erased and re-programmed, unlike PALs which have one-time-programmable fuses or EPLDs which can only slowly be erased with ultraviolet light through a glass window.
The ispGAL devices are a further improvement: they have JTAG port that supports in-system programmability (ISP), unlike earlier devices that need to be socketed to allow pulling them out of the system, then plugging in a freshly-programmed device. (That JTAG port also supports internal and board-level testing).<ref> "What is the difference between an ispGAL and a GAL device?" </ref>
SPLDs ...
CPLDs ... further improve density ... ...
FPGAs ... are even more dense -- entire CPUs can be implemented on a single FPGA IC. Some FPGAs have enough capacity to implement multiple CPUs ... but they have some drawbacks:
- most FPGAs reload their configuration on power-up, unlike CPLDs and SPLDs which are instant-on.
- CPLDs and SPLDs have more predictable timing delays
- SPLDs often have several second sources
- building something with some specific FPGA seems to force the designer to use one specific proprietary software tool on one of a narrow range of specific proprietary OSes.<ref>
Dieter Mueller 2004. "MT15". quote: "If there would be a standard with FPGAs/CPLDs ... allowing me to select between parts from different manufacturers with the same Pin_out while still working with the same (non_proprietary/open_source) software tools, this project would not exist." </ref>
- ...
GALs and CPLDs are still popular for retrocomputing projects
- (a) handling address decoding and other glue logic for "classic" 8-bit processors such as the 6502 and Z80
- (b) replacing the difficult-to-source 74181 and 74182 ALU chips used in many "discrete TTL CPUs", and perhaps further shrinking "discrete TTL CPUs" down to a few chips<ref>
"Tiny CPU in a CPLD". </ref><ref> Jim Mussared. "cpld-cpu: A simple CPU implemented by discrete CPLD components.". </ref><ref> Jim Mussared. "CPLD CPU: Part 1, Overview". quote: "Unfortunately the ALU chips (74181 and 74182) proved hard to source". quote: "However the idea is to make it possible to see what’s going on – every signal should have an LED on it." </ref><ref> Ed S. "OPC-1 CPU for CPLD". </ref><ref> "MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD". </ref>
Some open-source GAL programming tools (FIXME: very incomplete):
Many people use a Jam STAPL player (running on a laptop or Raspberry Pi) to send the "hex file" over a JTAG port to program a ispGAL or a FPGAs:
- Marcel Groothuis : "Altera Jam STAPL Player with support for 64-bit Windows versions and Raspberry Pi" : https://github.com/margro/jam-stapl
- vladermolaev: "jam2ftdi: Customization of Altera Jam STAPL Byte-Code Player Version 2.5 to work over USB for devices built on FTDI chips." https://github.com/vladermolaev/jam2ftdi
- Muhammet Şükrü Demir: "jam_bc_player: Jam STAPL Byte-Code Player for in-app programming Altera devices in embedded systems... such as STM32 or similar MCUs" https://github.com/dsm/jam_bc_player
- steieio: "Altera JAM STAPL Player" : https://github.com/steieio/altera-jam-player
- "The Jam STAPL Byte-Code Player is coded in the C programming language for 16 bit and 32 bit processors. A specific subset of the player source code also supports some 8 bit processors." https://www.intel.com/content/www/us/en/docs/programmable/683089/current/the-jam-stapl-byte-code-player.html
- "the Jam STAPL Web Site" (archived)
- "How-to: Programmable Logic Devices (CPLD)".
- "Parallel Port ATF and GAL Programmer".
- Richard Steven Walz. "GAL programming algorithms".
- "Manfred Winterhoff's GALBlast".
- Rune Baeverrud and Woody Johnson. "Build your own ByteBlaster".
- http://www.pldworld.com/_altera/html/ref/freecore/nosupport/nosupport.html
- "Simple GAL Programmer" 1999. Requires parallel port. Also programs PIC16F84.
Further reading
- Wikipedia: field-programmable gate array
- The Open Graphics Project wiki: The Open Graphics Project (OGP) is developing graphics cards with Free-licensed specifications and Free Software drivers. The FPGA development board OGD1, Revision B, uses a Xilinx® Spartan™-III XC3S4000 FPGA (primary FPGA) and a Lattice® LFXP10 non-volatile FPGA (PCI interface)
- "Project VGA": Home of the Low Budget, Open Source, VGA Compatible video card. Uses Xilinx Spartan 3 s400 FPGA.
