Difference between revisions of "Modulation Plugin"

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(New page: ==ToDos== *may move this project to opencircuit *make sure each components freq. response, to make sure the highest freq. *place DAC into this module board together, then only 4 wires(Vcc...)
 
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==ToDos==
 
==ToDos==
*may move this project to opencircuit
 
 
*make sure each components freq. response, to make sure the highest freq.  
 
*make sure each components freq. response, to make sure the highest freq.  
 
*place DAC into this module board together, then only 4 wires(Vcc, I2C clk, Gnd & I2C data) fr. host.  
 
*place DAC into this module board together, then only 4 wires(Vcc, I2C clk, Gnd & I2C data) fr. host.  
Line 10: Line 9:
  
 
==Objectives==
 
==Objectives==
*A plug-in for modulation which try to improve the technique to highest freq.
+
*The modulation module is used to deliver a digital output signal with the following characteristics:
*Software technique (Timer Interrupt controlling I2C DAC) can only achieve frequency response of about 1kHz
+
**Square wave
 +
**Variable frequency (>1kHz)
 +
**Variable amplitude (0V - 2.5V)
 +
*interface to MCU which do the control
 +
 
 +
 
 +
==Software Solution==
 +
*Timer Interrupt controlling I2C 10-bit DAC can only achieve frequency response of about 1kHz
 
**5byte/cmd
 
**5byte/cmd
 
**8bit/byte
 
**8bit/byte
 
**baudrate = 400kHz
 
**baudrate = 400kHz
 
**This yields 10kHz (0.1ms)
 
**This yields 10kHz (0.1ms)
**Set timer to 1ms (1kHz), so that 0.9ms can be used to process other tasks
+
**As OS context switch is 10ms, set timer to 1ms (1kHz), so that 0.9ms can be used to process other tasks
 
*Due to higher freq. response requirement, so using hardware to implement the clock
 
*Due to higher freq. response requirement, so using hardware to implement the clock
*interface to mcu which do the control
 
  
 +
==Hardware Solution==
 +
 +
===Circuit===
  
==Circuit for simulation by [http://www.falstad.com/circuit/ Paul Falstad's Web]==
+
===Circuit Simulation by [http://www.falstad.com/circuit/ Paul Falstad's Web]===
import the following
+
*Import the following
 
<pre><nowiki>
 
<pre><nowiki>
 
$ 1 5.0E-6 16.817414165184545 64 5.0 50
 
$ 1 5.0E-6 16.817414165184545 64 5.0 50
Line 67: Line 75:
  
  
==Components inside Cirsuit==
+
==Components inside Circuit==
  
 
===clk chip===
 
===clk chip===

Revision as of 00:02, 26 June 2008

ToDos

  • make sure each components freq. response, to make sure the highest freq.
  • place DAC into this module board together, then only 4 wires(Vcc, I2C clk, Gnd & I2C data) fr. host.
  • understand all components
  • call sample
  • draw circuit and PCB and grounding problem
  • test by real circuit and firmware


Objectives

  • The modulation module is used to deliver a digital output signal with the following characteristics:
    • Square wave
    • Variable frequency (>1kHz)
    • Variable amplitude (0V - 2.5V)
  • interface to MCU which do the control


Software Solution

  • Timer Interrupt controlling I2C 10-bit DAC can only achieve frequency response of about 1kHz
    • 5byte/cmd
    • 8bit/byte
    • baudrate = 400kHz
    • This yields 10kHz (0.1ms)
    • As OS context switch is 10ms, set timer to 1ms (1kHz), so that 0.9ms can be used to process other tasks
  • Due to higher freq. response requirement, so using hardware to implement the clock

Hardware Solution

Circuit

Circuit Simulation by Paul Falstad's Web

  • Import the following
$ 1 5.0E-6 16.817414165184545 64 5.0 50
w 128 256 144 256 0
w 16 256 64 256 0
g 16 352 16 368 0
v 64 64 112 64 0 0 40.0 2.5 0.0 0.0 0.5
w 112 128 144 128 0
w 64 128 16 128 0
w 16 128 16 256 0
v 64 256 128 256 0 2 1000.0 1.65 1.65 0.0 0.5
a 336 144 464 144 1 3.3 0.0
w 336 160 336 192 0
w 464 192 464 144 0
w 464 144 512 144 0
r 592 144 592 256 0 1000.0
g 592 352 592 368 0
w 512 144 592 144 0
w 336 192 352 192 0
w 432 192 464 192 0
v 64 128 112 128 0 1 1.0 1.25 1.25 0.0 0.5
w 16 256 16 288 0
w 16 288 16 352 0
w 592 256 592 352 0
g 272 352 272 368 0
w 272 128 336 128 0
w 176 256 176 144 0
r 272 224 272 288 0 1000.0
w 272 128 272 224 0
w 272 288 272 352 0
159 144 128 208 128 0
r 208 128 256 128 0 1000.0
w 256 128 272 128 0
w 144 256 176 256 0
r 336 224 336 288 0 1000.0
g 336 352 336 368 0
w 336 288 336 352 0
w 336 192 336 224 0
r 352 192 432 192 0 1000.0
o 4 64 0 34 2.5 7.8125E-4 0 -1
o 0 64 0 35 5.0 9.765625E-5 1 -1
o 11 64 0 34 2.5 0.0015625 2 -1


Components inside Circuit

clk chip

analog switch

op-amp buffer

  • OPA340